1. Field of the Invention
The present invention relates generally to an improved logic circuit and, more particularly, to an improved logic circuit having an improved disable circuit.
2. Description of the Prior Art
Shown by way of example in FIG. 1 is a logic circuit 10 which has been used in the past in bipolar integrated circuits to provide a predetermined output signal in response to simultaneously receiving one or more input signals. In the form shown in FIG. 1, the logic circuit 10 operates as an inverter by applying an output signal to an output terminal 12 which is the logical inverse of an input signal applied to an input terminal 14. As is common with such circuits, the logic circuit 10 is supplied with operating power from a power source (not shown) coupled to a power terminal 16 and a ground terminal 18.
In general, the logic circuit 10 is comprised of an input circuit 20 and a output circuit 22. In the input circuit 20, a PNP input device 24 selectively applies phase splitter drive current provided by a phase splitter drive current source resistor 26 to the output circuit 22 via a PN phase splitter driver diode 28, depending upon the input signal applied to the input terminal 14. More particularly, the input device 24 will assume a conducting state in response to a relatively low voltage input signal applied to the input terminal 14, so that substantially all of the phase splitter drive current provided by the phase splitter drive current source resistor 26 is shunted to the ground terminal 18. On the other hand, the input device 24 will assume a non-conducting state in response to a relatively high voltage input signal applied to the input terminal 14, so that the phase splitter drive current is applied to the output circuit 22 via the phase splitter driver diode 28. In the preferred form of such circuits, a Schottky input clamp diode 30 is interposed between the ground terminal 18 and the input terminal 14 to establish a low voltage input signal clamping level, and a Schottky phase splitter speed-up diode 32 is interposed between the output circuit 22 and the input terminal 14 to improve the response time of the output circuit 22 to changes in the state of the input signal applied to the input terminal 14.
In the output circuit 22, a Schottky-clamped NPN phase splitter device 34 selectively applies output drive current provided by an output drive current source resistor 36 to either a Schottky-clamped NPN active load driver device 38 or to a Schottky-clamped NPN active drive device 40, depending upon the state of the input circuit 20. More particularly, the phase splitter device 34 will assume a non-conducting state when the input device 24 of the input circuit 20 is in the conducting state and shunting all of the phase splitter drive current provided by the phase splitter drive current source resistor 26 to the ground terminal 18. In the non-conducting state of the phase splitter device 34, substantially all of the output drive current provided by the output drive current source resistor 36 is applied to the active load driver device 38. On the other hand, the phase splitter device 34 will assume a conducting state when the input device 24 of the input circuit 20 is in the non-conducting state, so that all of the phase splitter drive current is applied via the phase splitter driver diode 28 to the phase splitter device 34. In the conducting state of the phase splitter device 34, substantially all of the output drive current is applied to the active drive device 40.
In response to the output drive current applied thereto when the phase splitter device 34 is in the non-conducting state, the active load driver device 38 will assume a conducting state and provide active load drive current for an NPN active load device 42. In response to the active load drive current, the active load device 42 will assume a conducting state and will source output current to the output terminal 12 at a voltage very close to that applied by the power source (not shown) to the power terminal 16. In the preferred form of such circuits, an output current limiter resistor 44 is interposed between the power terminal 16 and the active load device 42 to establish a maximum output current level, and a pull-down resistor 46 is interposed between the ground terminal 18 and the base of the active load device 42 to improve the response time of the active load device 42 to changes in the state of the active load driver device 38.
In response to the output drive current applied thereto when the phase splitter device 34 is in the conducting state, the active drive device 40 will assume a conducting state and sink output current from the output terminal 12 at a voltage substantially the same as that applied by the power source (not shown) to the ground terminal 18. In the preferred form of such circuits, a "Baker" clamping circuit 48, comprised of an NPN clamp device 50, a base resistor 52 and a collector resistor 54, is interposed between the ground terminal 18 and the base of the active drive device 40 to improve the response characteristics of the active drive device 40.
In one preferred form of the logic circuit 10, a disable circuit 56 is provided to selectively disable the operation of the output circuit 22 by forcing the active load device 42 and the active drive device 40 simultaneously into the non-conducting state. In a typical form of the disable circuit 56, a Schottky-clamped NPN disable device 58, provided with disable drive current via a disable drive current source resistor 60, will assume a non-conducting state in response to a relatively high voltage disable signal applied to a disable terminal 62, so that the output drive current provided by the output drive current source resistor 36 is available for application to either the active load driver device 38 or to the active drive device 40 under the selective control of the phase splitter device 34. On the other hand, the disable device 58 will assume a conducting state in response to a relatively low voltage disable signal applied to the disable terminal 62, so that the output drive current provided by the output drive current source resistor 36 is shunted to the disable terminal 62, forcing the active load driver device 38 into the non-conducting state. Similarly, a second Schottky-clamped NPN transistor 64, provided with disable drive current via a disable drive current resistor 66, will assume a non-conducting state in response to a relatively high voltage disable signal applied to the disable terminal 62, so that the phase splitter drive current provided by the phase splitter drive current source resistor 26 is available for application to the phase splitter device 34 under the control of the input device 24. On the other hand, the disable device 64 will assume a conducting state in response to a relatively low voltage disable signal applied to the disable terminal 62, thereby shunting substantially all of the phase splitter drive current to the disable terminal 62, and forcing the phase splitter device 34 into the non-conducting state. Thus, both the active load device 42 and the active drive device 40 are forced simultaneously into the non-conducting state, and the output terminal 12 is placed into the high impedance state.
Although the logic circuit 10 has been generally satisfactory in many applications, the relatively high power dissipation of the logic circuit 10 in the disabled state is often undesirable. The logic circuit 10 is also limited to operation in the three-state mode, although many applications require operation in the open collector mode. In addition, it can be demonstrated that rapid changes in voltage at the output terminal 12 capacitively induce brief surges of drive current into the base of the active drive device 40, due to a phenomenon generally referred to as the Miller effect. For example, the transition of the active load device 42 from the non-conducting state to the conducting state, following the transition of the phase splitter device 34 from the conducting state to the non-conducting state, is often rapid enough to capacitively produce sufficient drive current to maintain the active drive device 40 in the conducting state for a brief period of time after the phase splitter device 34 has substantially assumed the non-conducting state. As a result, the active load device 42 must source a greater level of output current until the active drive device 40 actually assumes the non-conducting state. A similar problem arises in those applications where it is desired to couple the output terminal 12 to a communication bus (not shown) which is shared with other logic circuits. In this form, it is conventional to place all but one of the transmitting circuits in the disabled state to prevent transmission conflicts between circuits. However, even in the disabled state, the Miller-induced conduction of the active drive device 40 will impose a brief but significant current load on the transmitting circuit during each positive change in voltage at the output terminal 12.
A related logic circuit which exhibits one or more of these problems is described in the attached copy of U.S. Pat. No. 3,999,080. One other related logic circuit with some of these problems is described in the attached Preliminary Data Sheet on the Texas Instruments Octal General-Purpose Interface Bus Transceivers, Types SN75160 and SN75161.